Measuring Timing Errors in FPGA-based Circuits

FPGA-based platforms offer a unique and challenging platform for implementation of circuit-level timing-error detection and correction logic. If we operate FPGA designs beyond the conservative margins identified by the CAD tools, we can deliver substantial energy and performance improvements. In this paper we develop a strategy for monitoring timing errors in streaming FPGA circuits based on Razor-like shadow register insertion. Through a combination of careful calibration, hold timing control, critical path sampling and adaptation of the CAD flow, we design a robust, trustworthy error detection methodology for FPGA-based circuits. Our scheme can detect timing errors to deliver 39% energy reductions and 62% throughput improvements for the floating-point single-precision multiplier circuit with negligible overhead.